`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:41:22 09/08/2012 
// Design Name: 
// Module Name:    dis_peatonal 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module dis_peatonal(rst_i,value_i,peatonal_i,clk_i,segmentos_o
    );
	input peatonal_i,clk_i,rst_i;
	input [3:0] value_i;
	output [3:0] segmentos_o;
	reg [27:0] reloj;
	reg [3:0] peat;
	reg peatonal;
	
	initial begin 
		reloj=0;
		peat=0;
		peatonal=0;
	end
	
	assign segmentos_o=peat;
	
	always@(posedge clk_i)begin
		if(rst_i)begin
			peat<=0;
			reloj<=0;
		end
		else if(reloj==49999998&&peat!=0)begin
			peat<=peat-1;
			reloj<=0;
			peatonal<=0;
		end
		else if (reloj!=49999998&&peat!=0)begin
			reloj<=reloj+1;
		end
		else if(peatonal)begin
			peat<=value_i;
		end
		else if(peatonal_i)begin
			peatonal<=1;
		end
	
	end

endmodule
